The present invention provides a mechanism of assessing the performance of high-speed data buses. Accordingly, it is useful at this point to briefly review such data buses and the techniques that are currently used for assessing their performance. These topics will be discussed with reference to the accompanying Figures in which:
FIG. 1 is a block diagram of a typical receiver in a hybrid parallel-serial interface; and
FIG. 2 is a block diagram of a typical bit error testing device.
Modern software products (such as streaming video/audio etc.) have contributed to the ever-increasing demand for higher bandwidth data buses. High-speed data buses such as PCI-express, Hype Transport and RapidIO are replacing the traditional parallel PCI bus with a point-to-point communications system in which addressing information is packaged together with data and the resulting packets are transmitted over serial transmission lines. More recently, hybrid parallel-serial interfaces have been developed in which data is transmitted over multiple serial transmission lines operating in parallel.
Referring to FIG. 1, a receiver 10 in a hybrid parallel-serial interface typically comprises a differential I/O buffer 12, a clock and data recovery (CDR) circuit 14, a deserialiser or rate reduction block (DDR, QDR or ODR) 16, a deskewer 18 and a re-timing buffer 20. Since a timing signal is not generally transmitted in the data stream to a receiver, a CDR circuit 14 is used to regenerate a bit clock from the received data stream. Since individual serial transmission lines may have different time delays (because they are of different lengths etc.), the deskewer 18 is used to re-align data transmitted in parallel over multiple serial transmission lines. Finally, a reference clock 22 is used to control the timing of the CDR circuit 14, the deserialiser 16, deskewer 18 and the re-timing buffer 20.
Data transmitted at a double data rate (DDR) undergoes a transition at every clock edge. In other words, the data undergoes a transition at a rising clock edge and a falling clock edge. In contrast, data transmitted at a single data rate (SDR) undergoes a transition at every second clock edge (i.e. on either a rising clock edge or a falling clock edge).
The goal of a receiver in a digital data transmission system is to sample a received waveform at the point where its voltage and timing margins are as large as possible in order to minimize the risk of assigning an incorrect bit value to the sample. However, the increased data rates accommodated by high-speed data buses tend to accentuate irregularities in the signal stream. Furthermore, hardware analogue effects become more evident at higher data rates. Consequently, precise signal timing becomes more critical at higher data rates. One of the key metrics for quantifying the performance of a data transmission system is bit error rate (BER).
Referring to FIG. 2, a bit error testing circuit/device 40 typically comprises generator module 42 and a receiver module 44 which are respectively connectable to a transmitter Tx and a receiver Rx. The transmitter Tx is connected to the receiver Rx through data bus 46. The generator module 42 comprises a first test pattern generator LFSRGEN and the receiver module 44 comprises a second test pattern generator LFSRREC, comparator 48 and counter 50.
In use, the first test pattern generator LFSRGEN transmits a pre-defined test pattern PRBSGEN to the transmitter Tx. The transmitter Tx then transmits the test pattern through the data bus 46 to the receiver. Rx. The receiver Rx samples the bits from the received waveform and transmits the resulting bit sequence to the comparator 48. The second test pattern generator LFSRREC generates a confirmation pattern PRBSREC that matches the test pattern PRBSGEN generated by the first test pattern generator LFSRGEN. The second test pattern generator LFSRREC transmits the confirmation pattern PRBSREC to the comparator 48, which compares the confirmation pattern PRBSREC to the bit sequence received from the receiver Rx. The bit error rate is calculated as the number of bits that differ between the confirmation pattern PRBSREC and the bit sequence sampled from the waveform received by the receiver.
A pseudo-random bit sequence (PRBS) is a widely used test pattern for assessing bit error rates (BER). A PRBS is a particularly useful test pattern as it is an algorithmically determined, predictable and repeatable bit sequence that has the same statistical characteristics as a random sequence. These statistical characteristics mean that a PRBS can be readily used to simulate live traffic on a transmission line.
A PRBS can be generated by a linear feedback shift register (LFSR), in which some of the outputs from the register are fed back to its input through an XOR logic gate. By selecting different register lengths and feedback outputs it is possible to generate different output patterns. In particular, by correctly choosing the feedback outputs from an n-bit LFSR it is possible to generate a PRBS of length 2n−1, i.e. a maximal length sequence that includes all the possible permutations (patterns) of the n-bits, excluding the all-zeros pattern.
In light of the above discussion of PRBS test patterns and referring back to FIG. 2, for the sake of clarity the first test pattern generator LFSRGEN will be known henceforth as the generator LFSR. In addition, the test pattern PRBSGEN generated by the generator LFSR will be known henceforth as the generator PRBS. Similarly, the second test pattern generator LFSRREC and confirmation pattern PRBSREC generated therefrom will be respectively known henceforth as the receiver LFSR and the receiver PRBS.